1. Field of the Invention
The present invention relates to a semiconductor storage device and a production technique therefor, and in particular to a technique effectively applicable to the layout of power lines and the like for, for example, a semiconductor storage device such as static random access memory (SRAM).
2. Description of the Related Art
A one-bit data input/output circuit of, for example, a semiconductor storage device such as SRAM comprises a write/read circuit (i.e., a data unit) for data and a memory cell array for storing the data.
In a simple layout, it is conceivable to array memory cells in a 1-bit single array as in a semiconductor storage device according to the reference technique shown in FIG. 1A. For a product such as an application-specific integration circuit (ASIC), when considering both simplicity of use in the case of packaging it as a circuit macro for a semiconductor storage device and access performance, the memory cells are divided into four columns (i.e., a 4-column configuration) or eight columns (i.e., an 8-column configuration) as shown in FIG. 1B, and the memory cells are commonly used by equipping a column selection circuit corresponding to the plural-column structure.
Physically, the layout consists of a corresponding single set of write and read circuits placed on the upper or lower side of the memory cells which are divided into four columns (4-column) or eight columns (8-column) in the horizontal direction as shown in FIG. 1B.
The unit structure shown in FIG. 1A or FIG. 1B is arrayed for the number of required bits in the horizontal direction as shown in FIG. 1C. The left side of FIG. 1C shows the configuration of arraying the single set of circuits shown in FIG. 1A in a repeating pattern in the width direction, while the right side shows the configuration of arraying the single set of circuits shown in FIG. 1B in a repeating pattern in the width direction.
In addition to the data unit and memory cell array unit shown in FIG. 1C, the physical structure of the entire SRAM further includes a timer unit for generating a timing pulse to be supplied to each part of the SRAM, and a decode unit (Fdec unit) for driving word lines as shown in FIG. 1D.
Incidentally, while the overall structure shown in FIG. 1D shows the configuration of arraying a cell array on one side of the data unit, it is also possible to place the cell array symmetrically on the upper and lower sides, sandwiching the zone of the data unit. In such a case, the data unit will be equipped with a selection circuit for selecting either of the cell arrays on the upper and lower sides.
One bit of the data unit comprises a data input latch, a data output latch, an upper/lower selection circuit, a redundancy selection circuit, a column selection circuit, and the like as shown in FIG. 1C. In the actual layout, the individual circuits, by function, are packaged in a vertically oblong layout area.
On a transistor (Tr) level such as CMOS, the principal axis direction of a gate pattern (PC) constituted by polycrystal silicon or the like is the Y direction (i.e., the height direction of one-bit memory cells) as shown in FIGS. 1E and 1F, the power supply uses the X direction (i.e., the width direction of one-bit memory cells), the power supply line VDD is connected to a P channel (P-ch), and the power supply line VSS is connected to an N channel (N-ch).
Focusing on the packaging characteristics, the SRAM is laid out in a vertically oblong configuration in which a plurality of transistors (Tr), each of which is formed by setting the principal axis direction of the gate pattern in the vertical (Y) direction, are finely integrated in the Y direction as shown in layout areas L1 through L4 of FIG. 1E.
The structure of the semiconductor storage device according to the reference technique described above is faced with several technical problems as follows:
(1). For packaging transistors (Tr) by function in the vertically oblong layout area such as that shown in FIG. 2A, the number of power supply lines such as VDD and VSS is increased, suppressing the area around which a signal wiring can be drawn in the X (horizontal) direction as shown in FIG. 2B and increasing the limit of the drawing path of the signal lines.
(2). When a countermeasure is adopted for securing the area of signal wiring drawn around in the X (horizontal) direction so as to reduce the thickness of the power supply lines, as shown in the layout area L11 of FIG. 2A, the permissible power supply current is reduced and the power supply strength is accordingly reduced.
(3). Because a vertically oblong area is divided by a large number of power supply lines placed in the X direction to lay out transistors, extraneous areas are generated in the X direction as shown in the layout area L12 of FIG. 2A. Further, the share of power supply lines in the wiring layer in which the present power supply line exists is large and therefore the internal wiring of each circuit group needs to be placed in a layer of wiring as much lower than the wiring layer in which the power supply line exists as possible, as shown in the layout area L13 of FIG. 2A. Securing the drawing area L14 for the internal wiring as shown in FIG. 2B further reduces the packaging density of the transistors (Tr).
(4). If the direction of the power supply line is matched with the data unit as a result of giving a higher priority to the consistency of a layout in the timer unit placed at the center of the data unit as shown in FIG. 2C, a layout form different from that of the data unit in the layout area L21 of FIG. 2C is adopted and thereby layout efficiency is reduced.
Note that Laid-Open Japanese Patent Application Publication No. H10-65124 has disclosed a technique for commonizing a memory core, a basic logic gate, and the layout pattern of a transfer circuit with another product group in a semiconductor integrated circuit formed on a semiconductor chip by combining a memory core, basic logic gate, and transfer circuit capable of changing over the transfer pattern of data in real time.
While the technique according to this reference makes it possible to shorten the design time of various circuit products combining the memory core, basic logic gate and transfer circuit, none of the technical problems of the above described paragraphs (1) through (4), which are assigned to the present invention, are recognized.
Meanwhile, Laid-Open Japanese Patent Application Publication No. H10-50851 has disclosed a layout method comprising arraying cells in accordance with the logic of the target, each cell having no power supply line traversing within the circuit cell, possessing a minimum power supply terminal definition, and possessing a terminal definition including grid points of mutually different horizontal and vertical wiring tracks, and then carrying out power supply wiring by using a wiring layer corresponding to the principal axis of the wiring of the cell column.
Also, in the case of this reference, however, none of the technical problems of the above described paragraphs (1) through (4) is recognized.